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Multichannel, 24-Bit, 192 kHz, - DAC AD1833A
FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports 96 kHz Sample Rates on 6 Channels and 192 kHz on 2 Channels Supports 16-/20-/24-Bit Word Lengths Multibit - Modulators with Perfect Differential Linearity Restoration for Reduced Idle Tones and Noise Floor Data Directed Scrambling DACs--Least Sensitive to Jitter Differential Output for Optimum Performance DACs Signal-to-Noise and Dynamic Range: 110 dB -94 dB THD + N--6-Channel Mode -95 dB THD + N--2-Channel Mode On-Chip Volume Control per Channel with 1024-Step Linear Scale Software Controllable Clickless Mute Digital De-emphasis Processing Supports 256 fS, 512 f S, and 768 fS Master Clock Modes Power-Down Mode Plus Soft Power-Down Mode Flexible Serial Data Port with Right-Justified, Left-Justified, I 2S Compatible, and DSP Serial Port Modes Supports Packed Data Mode and TDM Mode 48-Lead LQFP Plastic Package APPLICATIONS DVD Video and Audio Players Home Theater Systems Automotive Audio Systems Set-Top Boxes Digital Audio Effects Processors FUNCTIONAL BLOCK DIAGRAM
DVD D 1 DVD D 2 ZERO FLAGS AVD D OUTLP1 OUTLN1 OUTLP2 OUTLN2 OUTLP3 OUTLN3 OUTRP3 OUTRN3 OUTRP2 OUTRN2 OUTRP1 OUTRN1
CDATA CLATCH CCLK MCLK RESET L/RCLK BCLK SDIN1 SDIN2 SDIN3 SOUT DATA PORT SPI PORT
INTERPOLATOR
DAC
INTERPOLATOR
DAC
INTERPOLATOR
DAC
FILTER ENGINE
INTERPOLATOR
DAC
INTERPOLATOR
DAC
INTERPOLATOR
DAC
AD1833A
FILTR FILTD DGND AGND
The AD1833A is fully compatible with all known DVD formats, accommodating word lengths of up to 24 bits at sample rates of 48 kHz and 96 kHz on all six channels while supporting a 192 kHz sample rate on two channels. It also provides the Redbook standard 50 ms/15 ms digital de-emphasis filters at sample rates of 32 kHz, 44.1 kHz, and 48 kHz. The AD1833A has a very flexible serial data input port that allows glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers, and sample rate converters. It can be configured in right-justified, left-justified, I2S, or DSP serial port compatible modes. The AD1833A accepts serial audio data in MSB first, twos complement format. The AD1833A can be operated from a single 5 V power supply; it also features a separate supply pin for its digital interface that allows it to be interfaced to devices using 3.3 V power supplies. The AD1833A is fabricated on a single monolithic integrated circuit and is housed in a 48-lead LQFP package for operation from -40C to +85C.
GENERAL DESCRIPTION
The AD1833A is a complete, high performance, single-chip, multichannel, digital audio playback system. It features six audio playback channels, each comprising a high performance digital interpolation filter, a multibit S-D modulator featuring Analog Devices' patented technology, and a continuous-time voltage-out analog DAC section. Other features include an on-chip clickless attenuator and mute capability for each channel, programmed through an SPI compatible serial control port.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD1833A-SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED*
Supply Voltages (AVDD, DVDDX) Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance Load Impedance
5V 25C 12.288 MHz, (8 Mode) Nominally 1 kHz, 0 dBFS (Full-Scale) 48 kHz 20 Hz to 20 kHz 24 Bits 100 pF 10 kW
*Performance is identical for all channels (except for the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Parameter
Min
Typ
Max
Unit
Test Conditions
ANALOG PERFORMANCE DIGITAL-TO-ANALOG CONVERTERS Dynamic Range (20 Hz to 20 kHz, -60 dBFS Input) with A-Weighted Filter AD1833AA AD1833AA AD1833AC Total Harmonic Distortion + Noise
106.5
SNR Interchannel Isolation DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ Method) Interchannel Phase Deviation Volume Control Step Size (1023 Linear Steps) Volume Control Range (Max Attenuation) Mute Attenuation De-emphasis Gain Error Full-Scale Output Voltage at Each Pin (Single-Ended) Output Resistance Measured Differentially Common-Mode Output Volts DAC INTERPOLATION FILTER--8 Mode (48 kHz) Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER--4 Mode (96 kHz) Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay
110.0 110.5 107.0 -95 -94 -95 -94 110 108 3 0.2 80 -120 0.1 0.098 +63.5 (0.098) -63.5 (0.098) 0.1 1 (2.8) 150 2.2
-89
dB dB dB dB dB dB dB dB dB % % ppm/C dB Degrees % dB (%) dB (%) dB V rms (V p-p) W V
fS = 96 kHz Two channels active Six channels active 96 kHz, two channels active 96 kHz, six channels active
24 70
0.01 510
21.768 kHz dB kHz dB ms 37.7 kHz dB kHz dB ms
55.034 70
0.03 160
DAC INTERPOLATION FILTER--2 Mode (192 kHz) Pass Band Pass-Band Ripple Stop Band 104.85 Stop-Band Attenuation 70 Group Delay
1 140
89.954 kHz dB kHz dB ms
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AD1833A
Parameter Min Typ Max Unit Test Conditions
DIGITAL I/O Input Voltage HI Input Voltage LO Output Voltage HI Output Voltage LO POWER SUPPLIES Supply Voltage (AVDD and DVDD1) Supply Voltage (DVDD2) Supply Current IANALOG Supply Current IDIGITAL Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins
Specifications subject to change without notice.
2.4 0.8 DVDD2 - 0.4 0.4 4.5 3.3 5 38.5 42 2 -60 -50 5.5 DVDD1 42 48
V V V V V V mA mA mA dB dB
Active Power-Down
DIGITAL TIMING (Guaranteed over -40 C to +85 C, AV
Parameter MASTER CLOCK AND RESET MCLK LO (All Modes)* tML MCLK HI (All Modes)* tMH tPDR PD/RST LO SPI PORT tCCH tCCL tCCP tCDS tCDH tCLS tCLH CCLK HI Pulsewidth CCLK LO Pulsewidth CCLK Period CDATA Setup Time CDATA Hold Time CLATCH Setup CLATCH Hold
DD
= DVDD = 5 V
Max
10%)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Comments 24 MHz clock, clock doubler bypassed 24 MHz clock, clock doubler bypassed
Min 15 15 20 20 20 80 10 10 10 10 15 15 10 10 10 15
To CCLK rising From CCLK rising To CCLK rising From CCLK rising
DAC SERIAL PORT tDBH BCLK HI BCLK LO tDBL tDLS L/RCLK Setup L/RCLK Hold tDLH SDATA Setup tDDS tDDH SDATA Hold TDM MODE MASTER BCLKTDM Delay tTMBD FSTDM Delay tTMFSD SDIN1 Setup tTMDDS tTMDDH SDIN1 Hold TDM MODE SLAVE BCLKTDM Frequency fTSB tTSBCH BCLKTDM High BCLKTDM Low tTSBCL FSTDM Setup tTSFS tTSFH FSTDM Hold SDIN1 Setup tTSDDS tTSDDH SDIN1 Hold AUXILIARY INTERFACE tAXLRD L/RCLK Delay tAXDD Data Delay tAXBD AUXBCLK Delay
*MCLK symmetry must be better than 60:40 or 40:60. Specifications subject to change without notice.
To BCLK rising From BCLK rising To BCLK rising From BCLK rising From MCLK rising From BCLKTDM rising To BCLKTDM falling From BCLKTDM falling
20 10 15 15 256 20 20 10 10 15 15 fS
ns ns ns ns
ns ns ns ns ns ns 10 10 20 ns ns ns
To BCLKTDM falling From BCLKTDM falling To BCLKTDM falling From BCLKTDM falling From BCLK falling From BCLK falling From MCLK rising
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AD1833A
tMH
MCLK
tML
PD/RST
tPDR
Figure 1. MCLK and RESET Timing
tCLS
CLATCH
tCCP
tCCH tCCL
tCLH
CCLK
tCDS tCDH
CIN
D15 D14
D9
D8
D0
Figure 2. SPI Port Timing
t DBH
BCLK
t DBL t DLS
L/RCLK
t DLH
t DDS
SDATA LEFT-JUSTIFIED MODE MSB MSB-1
t DDH
SDATA MODE
t DDS
MSB
I2S
t DDH
SDATA RIGHT-JUSTIFIED MODE
t DDS
MSB
t DDS
LSB
t DDH
t DDH
Figure 3. Serial Port Timing
MCLK
tTMBD
tTSBCL
tTSBCH
BCLKTDM
tTMFSD
FSTDM
tTSFS
tTSFH
tTMDDS
tTMDDH
SDIN1
MSB
tTSDDS
tTSDDH
Figure 4. TDM Master and Slave Mode Timing
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AD1833A
MCLK
tAXBD
AUXBCLK
tAXLRD
AUXL/RCLK
tAXDD
MSB AUX DATA
Figure 5. Auxiliary Interface Timing
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C, unless otherwise noted.)
AVDD, DVDDX to AGND, DGND . . . . . . . . -0.3 V to +6.5 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . -0.3 V to DVDD2 + 0.3 V Analog I/O Voltage to AGND . . . . . . -0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C
LQFP, qJA Thermal Impedance . . . . . . . . . . . . . . . . . 91C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
ORDERING GUIDE
Model AD1833AAST AD1833ACST EVAL-AD1833AEB AD1833AAST-REEL AD1833ACST-REEL
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description Low Profile Quad Flat Package Low Profile Quad Flat Package Evaluation Board Low Profile Quad Flat Package Low Profile Quad Flat Package
Package Option ST-48 ST-48 ST-48 ST-48
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1833A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD1833A
PIN CONFIGURATION
FILTD FILTR AGND OUTRP3 OUTRN3 OUTRP2 OUTRN2
36 OUTRP1 35 OUTRN1 34 AV DD 33 AV DD 32 AGND 31 AGND 30 AGND 29 DGND 28 DV DD2 27 RESET 26 ZERO1L 25 ZERO1R 13 14 15 16 17 18 19 20 21 22 23 24
OUTLN2
OUTLP2 OUTLN3 OUTLP3
48 47 46 45 44 43 42 41 40 39 38 37
OUTLP1 1 OUTLN1 2 AVDD 3 AVDD 4 AGND 5 AGND 6 AGND 7 DGND 8 DVDD1 9 ZEROA 10 ZERO3R 11 ZERO3L 12
PIN 1 IDENTIFIER
TOP VIEW (Not to Scale)
AVDD
AD1833A
BCLK MCLK SDIN1 SDIN2 SDIN3
ZERO2R CLATCH CDATA
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3, 4, 33, 34, 44 5, 6, 7, 30, 31, 32, 41 8, 29 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 35 36 37 38 39
Mnemonic IN/OUT OUTLP1 OUTLN1 AVDD AGND DGND DVDD1 ZEROA ZERO3R ZERO3L ZERO2R CLATCH CDATA CCLK L/RCLK BCLK MCLK SDIN1 SDIN2 SDIN3 SOUT ZERO2L ZERO1R ZERO1L RESET DVDD2 OUTRN1 OUTRP1 OUTRN2 OUTRP2 OUTRN3 O O
Description DAC 1 Left Channel Positive Output. DAC 1 Left Channel Negative Output. Analog Supply. Analog Ground. Digital Ground. Digital Supply to Core Logic. Flag to Indicate Zero Input on All Channels. Flag to Indicate Zero Input on Channel 3 Right. Flag to Indicate Zero Input on Channel 3 Left. Flag to Indicate Zero Input on Channel 2 Right. Latch Input for Control Data (SPI Port). Serial Control Data Input (SPI Port). Clock Input for Control Data (SPI Port). Left/Right Clock for DAC Data Input; FSTDM Input in TDM Slave Mode; FSTDM Output in TDM Master Mode. Bit Clock for DAC Data Input; BCLKTDM Input in TDM Slave Mode; BCLKTDM Output in TDM Master Mode. Master Clock Input. Data Input for Channel 1 Left/Right (Data Stream Input in TDM and Packed Modes). Data Input for Channel 2 Left/Right (L/RCLK Output to Auxiliary DAC in TDM Mode). Data Input for Channel 3 Left/Right (BCLK Output to Auxiliary DAC in TDM Mode). Auxiliary I2S Output (Available in TDM Mode). Flag to Indicate Zero Input on Channel 2 Left. Flag to Indicate Zero Input on Channel 1 Right. Flag to Indicate Zero Input on Channel 1 Left. Power-Down and Reset Control. Power Supply to Output Interface Logic. DAC 1 Right Channel Negative Output. DAC 1 Right Channel Positive Output. DAC 2 Right Channel Negative Output. DAC 2 Right Channel Positive Output. DAC 3 Right Channel Negative Output. -6- REV. 0
O O O O I I I I/O I/O I I I/O I/O O O O O I O O O O O
SOUT ZERO2L
CCLK L/RCLK
AD1833A
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. 40 42 43 45 46 47 48
Mnemonic IN/OUT OUTRP3 FILTR FILTD OUTLP3 OUTLN3 OUTLP2 OUTLN2 O
Description DAC 3 Right Channel Positive Output. Reference/Filter Capacitor Connection. Recommend 0.1 mF/10 mF decouple to analog ground. Filter Capacitor Connection. Recommend 0.1 mF/10 mF decouple to analog ground. DAC 3 Left Channel Positive Output. DAC 3 Left Channel Negative Output. DAC 2 Left Channel Positive Output. DAC 2 Left Channel Negative Output.
O O O O
DEFINITION OF TERMS Dynamic Range
Gain Error
The ratio of a full-scale input signal to the integrated input noise in the pass band (20 Hz to 20 kHz), expressed in decibels. Dynamic range is measured with a -60 dB input signal and is equal to (S/[THD + N]) +60 dB. Note that spurious harmonics are below the noise with a -60 dB input, so the noise level establishes the dynamic range. The dynamic range is specified with and without an A-Weight filter applied.
Signal to (Total Harmonic Distortion + Noise) [S/(THD + N)]
With a near full-scale input, the ratio of actual output to expected output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels.
Gain Drift
Change in response to a nearly full-scale input with a change in temperature, expressed as parts-per-million (ppm/C).
Crosstalk (EIAJ Method)
The ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels.
Pass Band
Ratio of response on one channel with a grounded input to a full-scale 1 kHz sine wave input on the other channel, expressed in decibels.
Power Supply Rejection
The region of the frequency spectrum unaffected by the attenuation of the digital decimator's filter.
Pass-Band Ripple
With no analog input, signal present at the output when a 300 mV p-p signal is applied to the power supply pins, expressed in decibels of full scale.
Group Delay
The peak-to-peak variation in amplitude response from equalamplitude input signal frequencies within the pass band, expressed in decibels.
Stop Band
The region of the frequency spectrum attenuated by the digital decimator's filter to the degree specified by stop-band attenuation.
Intuitively, the time interval required for an input pulse to appear at the converter's output, expressed in ms. More precisely, the derivative of radian phase with respect to the radian frequency at a given frequency.
Group Delay Variation
The difference in group delays at different input frequencies. Specified as the difference between the largest and the smallest group delays in the pass band, expressed in ms.
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AD1833A -Typical Performance Characteristics
0.010 0.008 0.006 0.004 0.002
dB
0.10 0.08 0.06 0.04 0.02
dB
0 -0.002 -0.004 -0.006 -0.008 -0.010 0 0.2 0.4 0.6 0.8 1.0 Hz 1.2 1.4 1.6 1.8 2.0 104
0 -0.02 -0.04 -0.06 -0.08 -0.10 0 0.5 1.0 1.5 2.0 Hz 2.5 3.0 3.5 104
TPC 1. Pass-Band Response, 8
Mode
TPC 4. Pass-Band Response, 4
Mode
10 0 -10 -20 -30
0.5 0.4 0.3 0.2 0.1
dB
dB
-40 -50 -60 -70 -80 -90 -100 2.00 2.05 2.10 2.15 2.20 2.25 Hz 2.30 2.35 2.40 2.45 2.50 104
0 -0.1 -0.2 -0.3 -0.4 -0.5 0 0.5 1.0 1.5 2.0 Hz 2.5 3.0 3.5 4.0 104
TPC 2. Transition Band Response, 8
Mode
TPC 5. 40 kHz Pass-Band Response, 4
Mode
10 0 0 -20 -40 -60 -10 -20 -30
dB
-80 -100 -120 -140 -160 0 0.5 1.0 1.5 Hz 2.0 2.5 3.0 105
dB
-40 -50 -60 -70 -80 -90 -100 4.0 4.2 4.4 4.6 4.8 5.0 Hz 5.2 5.4 5.6 5.8 6.0 104
TPC 3. Complete Response, 8
Mode
TPC 6. Transition Band Response, 4
Mode
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10
0
0
-20 -40 -60
dB
-10 -20 -30
-80 -100 -120 -140 -160
dB
-40 -50 -60 -70 -80 -90
0
0.5
1.0
1.5 Hz
2.0
2.5
3.0 105
-100 0.80
0.85
0.90
0.95
1.00 Hz
1.05
1.10
1.15
1.20 105
TPC 7. Complete Response, 4
Mode
TPC 9. Transition Band Response, 2
Mode
2.0
0
1.5
-20
1.0
-40
0.5
-60 dB
0 -0.5 -1.0 -1.5 -2.0 0 1 2 3 4 Hz 5 6 7 8 104
dB
-80 -100 -120 -140 -160 0 0.5 1.0 Hz 1.5 2.0 105
TPC 8. 80 kHz Pass-Band Response, 2
Mode
TPC 10. Complete Response, 2
Mode
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AD1833A
FUNCTIONAL DESCRIPTION Device Architecture
The AD1833A is a six-channel audio DAC featuring multibit sigma-delta (S-D) technology. The AD1833A features three stereo converters (providing six channels); each stereo channel is controlled by a common bit-clock (BCLK) and synchronization signal (L/RCLK).
General Overview
rate, only one doubling stage is used. In each case, the input sample frequency is increased to 384 kHz (IMCLK/64). The ZOH holds the interpolator samples for upsampling by the modulator. This is done at a rate 16 times the interpolator output sample rate.
Modulator
The AD1833A is designed to run with an internal MCLK (IMCLK) of 24.576 MHz and a modulator rate of 6.144 MHz (i.e., IMCLK/4). From this IMCLK frequency, sample rates of 48 kHz and 96 kHz can be achieved on six channels or 192 kHz can be achieved on two channels. The internal clock should never be run at a higher frequency but may be reduced to achieve lower sampling rates, i.e., for a sample rate of 44.1 kHz, the appropriate internal MCLK is 22.5792 MHz. The modulator rate scales in proportion with the MCLK scaling.
Interpolator
The modulator is a 6-bit, second order implementation and uses data scrambling techniques to achieve perfect linearity. The modulator samples the output of the interpolator stage(s) at a rate of (IMCLK/4).
OPERATING FEATURES SPI Register Definitions
The interpolator consists of as many as three stages of sample rate doubling and half-band filtering followed by a 16-sample zero order hold (ZOH). The sample rate doubling is achieved by zero stuffing the input samples, and a digital half-band filter is used to remove any images above the band of interest and to bring the zero samples to their correct values. The interpolator output must always be at a rate of IMCLK/64. Depending on the interpolation rates selected, one, two, or all three stages of doubling may be switched in. This allows for three different sample rate inputs for any given IMCLK. For an IMCLK of 24.576 MHz, all three doubling stages are used with a 48 kHz input sample rate; with a 96 kHz input sample rate, only two doubling stages are used; and with a 192 kHz input sample
The SPI port allows flexible control of the device's programmable functions. It is organized around nine registers: six individual channel volume registers and three control registers. Each write operation to the AD1833A SPI control port requires 16 bits of serial data in MSB-first format. The four most significant bits are used to select one of nine registers (seven register addresses are reserved), and the bottom 10 bits are written to that register. This allows a write to one of the nine registers in a single 16-bit transaction. The SPI CCLK signal is used to clock in the data. The incoming data should change on the falling edge of this signal and remain valid during the rising edge. At the end of the 16 CCLK periods, the CLATCH signal should rise to latch the data internally into the AD1833A (see Figure 2). The serial interface format used on the control port uses a 16-bit serial word, as shown in Table I. The 16-bit word is divided into several fields: Bits 15 through 12 define the register address, Bits 11 and 10 are reserved and must be programmed to 0, and Bits 9 through 0 are the data field (which has specific definitions, depending on the register selected).
Table I. Control Port Map
Register Address 152 14 13 12
NOTES 1 Must be programmed to zero. 2 Bit 15 = MSB.
Reserved 11
1
Data Field 9 8 7 6 5 4 3 2 1 0
10
Bit 15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 14 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Bit 13 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Bit 12 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Register Function DAC Control 1 DAC Control 2 DAC Volume 1 DAC Volume 2 DAC Volume 3 DAC Volume 4 DAC Volume 5 DAC Volume 6 DAC Control 3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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Table II. DAC Control Register 1 Function Data-Word Width Power-Down RESET Interpolator Mode
Address
Reserved1
De-emphasis
Serial Mode
15-12 0000
11 0
10 0
9-8 00 = None 01 = 44.1 kHz 10 = 32.0 kHz 11 = 48.0 kHz
7-5 000 = I S 001 = RJ 010 = DSP 011 = LJ 100 = Pack Mode 1 (256) 101 = Pack Mode 2 (128) 110 = TDM Mode 111 = Reserved
2
4-3 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = Reserved
2 0 = Normal 1 = PWRDWN
1-0 00 = 8 (48 kHz)2 01 = 2 (192 kHz)2 10 = 4 (96 kHz)2 11 = Reserved
NOTES 1 Must be programmed to zero. 2 For IMCLK = 24.576 MHz.
DAC CONTROL REGISTER 1 De-emphasis
DAC Word Width
The AD1833A has a built-in de-emphasis filter that can be used to decode CDs that have been encoded with the standard Redbook 50 ms/15 ms emphasis response curve. Three curves are available, one each for 32 kHz, 44.1 kHz, and 48 kHz sampling rates. The filters may be selected by writing to Control Bits 9 and 8 in DAC Control Register 1 (see Table III).
Table III. De-emphasis Settings
The AD1833A will accept input data in three separate wordlengths--16 bits, 20 bits, and 24 bits. The word length may be selected by writing to Control Bits 4 and 3 in DAC Control Register 1 (see Table V).
Table V. Word Length Settings
Bit 4 0 0 1 1
Power-Down Control
Bit 3 0 1 0 1
Word Length 24 Bits 20 Bits 16 Bits Reserved
Bit 9 0 0 1 1
Bit 8 0 1 0 1
De-emphasis Disabled 44.1 kHz 32 kHz 48 kHz
The AD1833A can be powered down by writing to Control Bit 2 in DAC Control Register 1 (see Table VI).
Table VI. Power-Down Control
Data Serial Interface Mode
The AD1833A's serial data interface is designed to accept data in a wide range of popular formats including I2S, right-justified (RJ), left-justified (LJ), and flexible DSP modes. The L/RCLK pin acts as the word clock (or frame sync) to indicate sample interval boundaries. The BCLK defines the serial data rate while the data is input on the SDIN1-SDIN3 pins. The serial mode settings may be selected by writing to Control Bits 7 through 5 in the DAC Control Register 1 (see Table IV).
Table IV. Data Serial Interface Mode Settings
Bit 2 0 1
Interpolator Mode
Power-Down Setting Normal Operation Power-Down Mode
Bit 7 0 0 0 0 1 1 1 1
Bit 6 0 0 1 1 0 0 1 1
Bit 5 0 1 0 1 0 1 0 1
Serial Mode I 2S Right Justify DSP Left Justify Packed Mode 1 (256) Packed Mode 2 (128) TDM Mode Reserved
The AD1833A's DAC interpolators can be operated in one of three modes--8 , 4 , or 2 -- then correspond to 48 kHz, 96 kHz, and 192 kHz modes, respectively (for IMCLK = 24.576 MHz). The interpolator mode may be selected by writing to Control Bits 1 and 0 in DAC Control Register 1 (see Table VII).
Table VII. Interpolator Mode Settings
Bit 1 0 0 1 1
Bit 0 0 1 0 1
Interpolator Mode 8x (48 kHz)* 2x (192 kHz)* 4x (96 kHz)* Reserved
*For IMCLK = 24.576 MHz.
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AD1833A
DAC CONTROL REGISTER 2
DAC Control Register 2 contains individual channel mute controls for each of the six DACs. Default operation (bit = 0) is muting off. Bits 9 through 6 of Control Register 2 are reserved and should be programmed to zero (see Table VIII).
DAC CONTROL REGISTER 3 Stereo Replicate
The AD1833A allows the stereo information on Channel 1 (SDIN1--Left 1 and Right 1) to be copied to Channels 2 and 3 (Left/Right 2 and Left/Right 3). These signals can be used in an external summing amplifier to increase potential signal SNR. Stereo replicate mode can be enabled by writing to control Bit 5 (see Table XI). Note that replication is not reflected in the zero flag status.
Table VIII. DAC Control Register 2
Function Address 15-12 0001 Reserved* 11 0 10 0 Reserved* 9-6 0 5 Channel 6 0 = Mute Off 1 = Mute On 4 3 Mute Control 2 Channel 3 0 = Mute Off 1 = Mute On 1 0
Channel 5 Channel 4 0 = Mute Off 0 = Mute Off 1 = Mute On 1 = Mute On
Channel 2 Channel 1 0 = Mute Off 0 = Mute Off 1 = Mute On 1 = Mute On
*Must be programmed to zero.
Table IX. Muting Control
Bit 5 X X X X X 1
Bit 4 X X X X 1 X
Bit 3 X X X 1 X X
Bit 2 X X 1 X X X
Bit 1 X 1 X X X X
Bit 0 1 X X X X X
Muting Mute Channel 1 Mute Channel 2 Mute Channel 3 Mute Channel 4 Mute Channel 5 Mute Channel 6
Table X. DAC Control Register 3 Function Address 15-12 1000 Stereo Replicate Reserved* Reserved* (192 kHz) 11 0 10 0 9-6 0 5 0 = Normal 1 = Replicate MCLK Select 4-3 00 = IMCLK = MCLK 01 = IMCLK = MCLK 10 = IMCLK = MCLK 2 1 2 /3 Zero Detect 2 0 = Active High 1 = Active Low Reserved* 1 0 TDM Mode 0 0 = Master 1 = Slave
*Must be programmed to zero.
Table XI. Stereo Replicate
Bit 5 0 1
Stereo Mode Normal Channel 1 Data Replicated on Channels 2 and 3
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AD1833A
MCLK Select
The AD1833A allows the matching of available external MCLK frequencies to the required internal MCLK rate. The MCLK modification factor can be selected from 2, 1, or 2/3 by writing to Bit 4 and Bit 3 of Control Register 3. Internally, the AD1833A requires an MCLK of 24.576 MHz for sample rates of 48 kHz, 96 kHz, and 192 kHz. In the case of 48 kHz data with an MCLK of 256 fS, a clock doubler is used, whereas with an MCLK of 768 fS, a divide-by-3 block ( 3) is first implemented followed by a clock doubler. With an MCLK of 512 fS, the MCLK is passed through unmodified (see Table XII).
Table XII. MCLK Settings
a global zero flag that indicates all channels contain zero data. The polarity of the zero signal is programmable by writing to Control Bit 2 (see Table XIII). In right-justified mode, the six individual channel flags are best used as three stereo zero flags by combining pairs of them through suitable logic gates. Then, when both the left and right inputs are zero for 1024 clock cycles, i.e., a stereo zero input for 1024 sample periods, the combined result of the two individual flags will become active, indicating a stereo zero.
Table XIII. Zero Detect
Bit 2 0 1
Channel Zero Status Active High Active Low
Bit 4 0 0 1 1
Bit 3 0 1 0 1
Modification Factor MCLK 2 Internally MCLK 1 Internally MCLK 2/3 Internally Reserved
DAC Volume Control Registers
Channel Zero Status
The AD1833A provides individual logic output status indicators when zero data is sent to a channel for 1024 or more consecutive sample periods in all modes except right-justified. There is also
The AD1833A has six volume control registers, one for each of the six DAC channels. Volume control is exercised by writing to the relevant register associated with each DAC. This setting is used to attenuate the DAC output. Full-scale setting (all 1s) is equivalent to zero attenuation (see Table XV).
Table XIV. MCLK vs. Sample Rate Selection
Sampling Rate fS (kHz) 32 64 128 44.1 88.2 176.4 48 96 192
Interpolator Mode Required 8 4 2 8 4 2 8 4 2
Internal MCLK Required (MHz) 16.384
Suitable External MCLK Frequencies (MHz) MCLK 2 MCLK 1 MCLK 8192 16.384 24.576
2
/3
22.5792
11.2896
22.5792
33.8688
24.576
12.288
24.576
36.864
Table XV. Volume Control Registers
Address 15-12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1
Reserved* 11 0 10 0
Volume Control 9-0 Channel 1 Volume Control (OUTL1) Channel 2 Volume Control (OUTR1) Channel 3 Volume Control (OUTL2) Channel 4 Volume Control (OUTR2) Channel 5 Volume Control (OUTL3) Channel 6 Volume Control (OUTR3)
*Must be programmed to zero.
REV. 0
-13-
AD1833A
I2S Timing
I2S timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The L/RCLK is low for the left channel and high for the right channel. A bit clock running at 64 fS is used to clock in the data. There is a delay of 1 bit clock from the time the L/RCLK signal changes state to the first bit of data on the SDINx lines. The data is written MSB first and is valid on the rising edge of the bit clock.
Left-Justified Timing
to clock in the data. The first bit of data appears on the SDINx lines when the L/RCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock.
Right-Justified Timing
Left-justified (LJ) timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The L/RCLK is high for the left channel and low for the right channel. A bit clock running at 64 fS is used
Right-justified (RJ) timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The L/RCLK is high for the left channel and low for the right channel. A bit clock running at 64 fS is used to clock in the data. The first bit of data appears on the SDINx 8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before L/RCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock.
L/RCLK INPUT BCLK INPUT SDATA INPUT
MSB -1 MSB -2
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB +2
LSB +1
LSB
MSB
MSB MSB -1 -2
LSB +2
LSB +1
LSB
MSB
Figure 6. I 2S Timing Diagram
L/RCLK INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK INPUT SDATA INPUT
MSB -1 MSB -2 LSB +2 LSB +1 MSB -1 MSB -2 LSB +2 LSB +1 MSB -1
MSB
LSB
MSB
LSB
MSB
Figure 7. Left-Justified Timing Diagram
L/RCLK INPUT BCLK INPUT SDATA INPUT
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
MSB -1
MSB -2
LSB +2
LSB +1
LSB
MSB
MSB -1
MSB -2
LSB +2
LSB +1
LSB
Figure 8. Right-Justified Timing Diagram
-14-
REV. 0
AD1833A
TDM Mode Timing--Interfacing to a SHARC (R)
In TDM mode, the AD1833A can be the master or slave, depending on Bit 0 in Control Register 3. In master mode, it generates a frame sync signal (FSTDM) on its L/RCLK pin and a bit clock (BCLKTDM) on its BCLK pin, whereas in slave mode it expects these signals to be provided. These signals are used to control the data transmission from the SHARC. The bit clock must run at a frequency of IMCLK/2 and the interpolation mode must be set to 8 , which limits TDM mode to frequencies of 48 kHz or less. In this mode, all data is written on the rising edge of the bit clock and read on the falling edge of the bit clock. The frame starts with a frame sync at the rising edge of the bit clock. The SHARC then starts outputting data on the next rising edge of the bit clock. Each channel is given a 32-bit clock slot, and the data is left-justified and uses 16, 20, or 24 of the 32 bits. An enlarged diagram detailing this is provided (see Figure 9). The data is sent from the SHARC to the AD1833A on the SDIN1 pin and provided in the following order: MSB first--Internal DACL0, Internal DACL1, Internal DACL2, AUX DACL0, Internal DACR0, Internal DACR1, Internal DACR2, and AUX
DACR0. The data is written on the rising edge of the bit clock and read by the AD1833A on the falling edge of the bit clock. The left and right data destined for the auxiliary DAC is sent in standard I2S format in the next frame using the SDIN2, SDIN3, and SOUT pins as the L/RCLK, BCLK, and SDATA pins, respectively, for communicating with the auxiliary DAC.
DSP Mode Timing
DSP mode timing uses the rising edge of the frame sync signal on the L/RCLK pin to denote the start of the transmission of a data-word. Note that for both left and right channels, a rising edge is used; therefore in this mode, there is no way to determine which data is intended for the left channel and which is intended for the right. The DSP writes data on the rising edge of BCLK and the AD1833A reads it on the falling edge. The DSP raises the frame sync signal on the rising edge of BCLK and then proceeds to transmit data, MSB first, on the next rising edge of BCLK. The data length can be 16, 20, or 24 bits. The frame sync signal can be brought low any time at or after the MSB is transmitted, but must be brought low at least one BCLK period before the start of the next channel transmission.
FSTDM
BCLKTDM
INTERNAL DAC L0
INTERNAL DAC L1
INTERNAL DAC L2
AUXILIARY DAC L0
INTERNAL DAC R0
INTERNAL DAC R1
INTERNAL DAC R2
AUXILIARY DAC R0
BCLKTDM
24-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB +8
LSB +7
LSB +6
LSB +5
LSB +4
LSB +3
LSB +2
LSB +1
LSB
20-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB +4
LSB +3
LSB +2
LSB +1
LSB
16-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB
Figure 9. TDM Mode Timing
L/RCLK
BCLK
SDATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
MSB -5
MSB -6
MSB
MSB -1
MSB -2
MSB -3
MSB -4
MSB -5
MSB -6
MSB
32 BCLKs
32 BCLKs
Figure 10. DSP Mode Timing
REV. 0
-15-
AD1833A
Packed Mode 128 Packed Mode 256
In Packed Mode 128, all six data channels are packed into one sample interval on one data pin. The BCLK runs at 128 fS; therefore, there are 128 BCLK periods in each sample interval. Each sample interval is broken into eight time slots: six slots of 20 BCLK and two of 4 BCLK. In this mode, the data length is restricted to a maximum of 20 bits. The three left channels are written first, MSB first, and the data is written on the falling edge of BCLK. After the three left channels are written, there is a space of four BCLK, and then the three right channels are written. The L/RCLK defines the left and right data transmission; it is high for the three left channels and low for the three right channels.
L/RCLK
In Packed Mode 256, all six data channels are packed into one sample interval on one data pin. The BCLK runs at 256 fS; therefore, there are 256 BCLK periods in each sample interval, and each sample interval is broken into eight time slots of 32 BCLK each. The data length can be 16, 20, or 24 bits. The three left channels are written first, MSB first, and the data is written on the falling edge of BCLK with a one BCLK period delay from the start of the slot. After the three left channels are written, there is a space of 32 BCLK, and then the three right channels are written. The L/RCLK defines the left and right data transmission; it is low for the three left channels and high for the three right channels.
BCLK
DATA
SLOT 1 LEFT 0
SLOT 2 LEFT 1
SLOT 3 LEFT 2
BLANK SLOT 4 SCLK
SLOT 4 RIGHT 0
SLOT 5 RIGHT 1
SLOT 6 RIGHT 2
BLANK SLOT 4 SCLK
BCLK
20-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB +4
LSB +3
LSB +2
LSB +1
LSB
16-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB
Figure 11. Packed Mode 128
L/RCLK
BCLK
DATA
SLOT 1 LEFT 0
SLOT 2 LEFT 1
SLOT 3 LEFT 2
SLOT 4 RIGHT 0
SLOT 5 RIGHT 1
SLOT 6 RIGHT 2
BCLK
24-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB +8
LSB +7
LSB +6
LSB +5
LSB +4
LSB +3
LSB +2
LSB +1
LSB
20-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB +4
LSB +3
LSB +2
LSB +1
LSB
16-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB
Figure 12. Packed Mode 256
-16-
REV. 0
AD1833A
0
11k VOUT- 11k 3.81k 270pF NPO 560pF NPO VOUT+ 1.50k 5.62k 5.62k
68pF NPO
-20
6 OP275 5 7 604 2.2nF NPO VFILTOUT
dBR
-40
100pF NPO
-60 -80
150pF NPO
-100
-120 -140 0 20 40 60 kHz 80 100 120
Figure 13. Suggested Output Filter Schematic
Figure 16. Dynamic Range for 37 kHz @ -60 dBFS, 110 dB, Triangular Dithered Input
0 -20
0 -20
-40
-40
-60
-60
dBR
dBR
-80 -100
-80 -100
-120 -140 0 2 4 6 8 10 kHz 12 14 16 18 20
-120 -140
0
20
40
60 kHz
80
100
120
Figure 14. Dynamic Range for 1 kHz @ -60 dBFS, 110 dB, Triangular Dithered Input
Figure 17. Input 0 dBFS @ 37 kHz, BW 20 Hz to 120 kHz, SR 96 kHz, THD + N -95 dBFS
0 -20
0 -20 -40 -60
-40
-60
dBR
dBV
-80 -100 -120 -140 0 2 4 6 8 10 kHz 12 14 16 18 20
-80 -100 -120 -140 -160
0
2
4
6
8
10 kHz
12
14
16
18
20
Figure 15. Input 0 dBFS @ 1 kHz, BW 20 Hz to 20 kHz, SR 48 kHz, THD + N -95 dBFS
Figure 18. Noise Floor for Zero Input, SR 48 kHz, SNR 110 dBFS A-Weighted
REV. 0
-17-
AD1833A
-60 -20 -30 -70 -40 -50 -60
dBR dBR
-80
-90
-70 -80
-100
-90 -100 -110
-110
-120 -100 -90
-80
-70
-60
-50 -40 dBFS
-30
-20
-10
0
-120 -100 -90
-80
-70
-60
-50 -40 dBFS
-30
-20
-10
0
Figure 19. THD + N Amplitude vs. Input Amplitude, Input 1 kHz, SR 48 kHz, 24-Bit
Figure 20. THD + N Ratio vs. Input Amplitude, Input 1 kHz, SR 48 kHz, 24-Bit
-18-
REV. 0
AD1833A
DVDD -INTF 5V 10 F + 0.1 F 10 F + 0.1 F 10 F + 0.1 F 10 F + 0.1 F 10 F + 0.1 F 4 33 3 34 44 AVD D 1 AVD D 2 AVD D AVD D AVD D 1 OUTLP1 2 OUTLN1 47 OUTLP2 OUTLN2 48 45 OUTLP3 OUTLN3 46 36 OUTRP1 35 OUTRN1 38 OUTRP2 37 OUTRN2 40 OUTRP3 OUTRN3 39 GND GND GND GND FILTR FILTD 42 43 + 0.1 F 10 F 0.1 F + 10 F L1+ L1- L2+ L2- L3+ L3- R1+ R1- R2+ R2- R3+ R3- 10 F + 0.1 F AVDD 5V
10 F + DVD D 0.1 F AVD D 10 F CLATCH CDATA CCLK 26 SDATA 11 FSYNC 12 SCK 19 MCK 0.1 F 9 28 DVD D 1 CLATCH 15 CDATA 16 CCLK 17 18 20 21 22 23 19 L/RCLK BCLK SDIN1 SDIN2 SDIN3 SOUT MCLK DVD D 2 14
22 VA+ 10nF 75RO 10nF 10 RXN 9 RXP
7 VD+
PAL
AD1833A
1k
DGND1
DGND2
GND
47nF
21 8
AGND DGND
CO/EO CA/E1 CB/E2 CC/F0 CD/F1 CE/F2 SEL CS12/FCK
6 5 4 3 2 27 16 13
8 29
7 30
GND 5V L5 10k 3 DVD D U5 TORX173
6 31 5 32 41
0.1 F
5 6 2 4
SHLD1 SHLD1 SHLD1 SHLD1
OUT
Figure 21. Example Digital Interface
REV. 0
-19-
GND 1
23 M0 24 20 M1 18 FILT M2 17 M3 DIR-CS8414 1 C 14 U 15 CBL 28 VERF ERF 25
AD1833A
OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] 1.4 mm Thick (ST-48)
Dimensions shown in millimeters
1.60 MAX 0.75 0.60 0.45
PIN 1 INDICATOR 9.00 BSC
48 1 37 36
1.45 1.40 1.35
0.20 0.09
SEATING PLANE
TOP VIEW
(PINS DOWN)
7.00 BSC
0.15 0.05
SEATING PLANE
7 3.5 0 0.08 MAX COPLANARITY
VIEW A
12 13 24 25
VIEW A
ROTATED 90 CCW
0.50 BSC
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BBC
-20-
REV. 0
C02336-0-5/03(0)

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